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LTC6915 Zero Drift, Precision Instrumentation Amplifier with Digitally Programmable Gain
FEATURES
s s s s s s s s s s
DESCRIPTIO
14 Levels of Programmable Gain 125dB CMRR Independent of Gain Gain Accuracy 0.1% (Typ) Maximum Offset Voltage of 10V Maximum Offset Voltage Drift: 50nV/C Rail-to-Rail Input and Output Parallel or Serial (SPI) Interface for Gain Setting Supply Operation: 2.7V to 5.5V Typical Noise: 2.5VP-P (0.01Hz to 10Hz) 16-Lead SSOP and 12-Lead DFN Packages
The LTC(R)6915 is a precision programmable gain instrumentation amplifier. The gain can be programmed to 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, or 4096 through a parallel or serial interface. The CMRR is typically 125dB with a dual 5V supply with any programmed gain. The offset is below 10V with a temperature drift of less than 50nV/C. The LTC6915 uses charge balanced sampled data techniques to convert a differential input voltage into a single ended signal that is in turn amplified by a zero-drift operational amplifier. The differential inputs operate from rail-to-rail and the single-ended output swings from rail-to-rail. The LTC6915 can be used in single power supply applications as low as 2.7V, or with dual 5V supplies. The LTC6915 is available in a 16-lead SSOP package and a 12-lead DFN surface mount package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s s s s s
Thermocouple Amplifiers Electronic Scales Medical Instrumentation Strain Gauge Amplifier High Resolution Data Acquisition
TYPICAL APPLICATIO
Differential Bridge Amplifier with Gain Programmed through the Serial Interface
LTC6915 SSOP PACKAGE 3 IN + 3V 2 IN R < 10k RESISTOR ARRAY REF 13 11 PARALLEL_SERIAL 4-BIT LATCH HOLD_THRU 5 V+ 16 3V 0.1F Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 8-BIT SHIFT-REGISTER SHDN DGND V 1 10
_
+
OUT 15 CS CH
-
CF
MUX 6 CS(D0) 7 DIN(D1) 8 CLK(D2) 9 DOUT(D3)
P TO OTHER DEVICES
U
SENSE 14
-4
6915 TA01
U
U
6915f
1
LTC6915
ABSOLUTE AXI U RATI GS
Total Supply Voltage (V + to V -) ............................... 11V Input Current ...................................................... 10mA |VIN+ - VREF| ....................................................... 5.5V |VIN- - VREF| ....................................................... 5.5V |V+ - VDGND| ....................................................... 5.5V |VDGND - V -| ....................................................... 5.5V Digital Input Voltage ......................................... V - to V + Operating Temperature Range LTC6915C .............................................-0C to 70C
PACKAGE/ORDER I FOR ATIO
TOP VIEW IN- IN+ V- CS(D0) DIN(D1) CLK(D2) 1 2 3 4 5 6 12 V + 11 OUT 10 REF 9 8 7 PARALLEL_SERIAL DGND DOUT(D3)
ORDER PART NUMBER LTC6915CDE LTC6915IDE DFN PART MARKING 6915 6915I
DE12 PACKAGE 12-LEAD (4mm x 3mm) PLASTIC DFN UNDERSIDE METAL CONNECTED TO V-
TJMAX = 125C, JA = 160C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
SYMBOL V+ = 3V, V - PARAMETER = 0V, VREF = 200 mV Gain Error (Note 2) Gain Error (Note 2) Gain Error (Note 2) Gain Error (Note 2) Gain Nonlinearity VOS Input Offset Voltage (Note 3) Average Input Offset Drift (Note 3) IB IOS Average Input Bias Current (Note 4) Average Input Offset Current (Note 4) AV = 1 (RL =10k) AV = 2 to 32 (RL = 10k) AV = 64 to 1024 (RL = 10k) AV = 2048, 4096 (RL = 10k) AV = 1 VCM = 200mV TA = -40C to 85C TA = 85C to 125C VCM = 1.2V VCM = 1.2V
q q q q q q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS
2
U
U
W
WW
U
W
(Note 1)
LTC6915I .............................................-40C to 85C LTC6915H .........................................-40C to 125C Junction Temperature (GN Package) ................................................... 150C (DFN Package).................................................. 125C Storage Temperature (GN Package) ....................................-65C to 150C (DFN Package)...................................-65C to 125C Lead Temperature (Soldering 10 sec)................... 300C
TOP VIEW SHDN 1 IN - 2 IN + 3 V- 4 HOLD_THRU 5 CS(D0) 6 DIN(D1) 7 CLK(D2) 8 16 V+
ORDER PART NUMBER LTC6915CGN LTC6915IGN LTC6915HGN GN PART MARKING 6915 6915I 6915H
15 OUT 14 SENSE 13 REF 12 NC 11 PARALLEL_SERIAL 10 DGND 9 DOUT(D3)
GN PACKAGE 16-LEAD NARROW PLASTIC SSOP
TJMAX = 150C, JA = 135C/W
MIN -0.075 -0.5 -0.6 -1
TYP 0 0 -0.1 -0.2 3 -3
MAX 0.075 0.5 0.6 1.0 15 10 50 100
UNITS % % % % ppm V nV/C nV/C nA nA
5 1.5
10 3
6915f
LTC6915
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
SYMBOL CMRR PARAMETER Common Mode Rejection Ratio CONDITIONS AV = 1024, VCM = 0V to 3V, LTC6915C AV = 1024, VCM = 0.1V to 2.9V, LTC6915I AV = 1024, VCM = 0V to 3V, LTC6915I AV = 1024, VCM = 0.1V to 2.9V, LTC6915H AV = 1024, VCM = 0V to 2.97V, LTC6915H VS = 2.7V to 6V Sourcing 200A Sourcing 2mA Sinking 200A Sinking 2mA No Load at OUT, VCM = 200mV No Load at OUT, Capacitive Load at DOUT (CL) = 15pF, Continuous CLK Frequency = 4MHz, CS= LOW, Gain Control Code = 0001 VSHDN = 2.7V (Hardware Shutdown) VSHDN = 1V, Gain Control Code = 0000 (Software Shutdown )
q q q q q q q q q q q q
ELECTRICAL CHARACTERISTICS
V+ = 3V, V - = 0V, VREF = 200 mV
MIN 100 100 95 100 85 110 2.95 2.75
TYP 119 119 119
MAX
UNITS dB dB dB dB dB dB V V
PSRR
Power Supply Rejection Ratio (Note 5) Output Voltage Swing High (Referenced to V-) Output Voltage Swing Low (Referenced to V-) Supply Current, Parallel Mode Supply Current, Serial Mode (Note 6)
116 2.98 2.87 18 130 0.88 1.1 50 300 1.3 1.65
mV mV mA mA
Supply Current Shutdown
q q q q q
1 125 2.7
4 180
A A V
SHDN Input High SHDN Input Low SHDN and HOLD_THRU Input Current (Note 2) Internal Op Amp Gain Bandwidth Slew Rate Internal Sampling Frequency V+ = 5V, V- = 0V, VREF = 200mV Gain Error (Note 2) Gain Error (Note 2) Gain Error (Note 2) Gain Error (Note 2) Gain Nonlinearity VOS Input Offset Voltage (Note 3) Average Input Offset Drift (Note 3) Average Input Bias Current (Note 4) IOS CMRR Average Input Offset Current (Note 4) Common Mode Rejection Ratio AV = 1 (RL = 10k) AV = 2 to 32 (RL= 10k) AV = 64 to 1024 (RL = 10k) AV = 2048, 4096 (RL = 10k) AV = 1 VCM = 200mV TA = -40C to 85C TA = 85C to 125C VCM = 1.2V VCM = 1.2V AV = 1024, VCM = 0V to 5V, LTC6915C AV = 1024, VCM = 0.1V to 4.9V, LTC6915I AV = 1024, VCM = 0V to 5V, LTC6915I AV = 1024, VCM = 0.1V to 4.9V, LTC6915H AV = 1024, VCM = 0V to 4.97V, LTC6915H VS = 2.7V to 6V Sourcing 200A Sourcing 2mA Sinking 200A Sinking 2mA
1 5 200 0.2 -0.5 3 0 0 -0.1 -0.2 3 -3 0.075 0.5 0.6 1 15 10 50 100 5 1.5 105 105 95 100 85 110 4.95 4.80 125 125 125 10 3
V A kHz V/s kHz % % % % ppm V nV/C nV/C nA nA dB dB dB dB dB dB V V
q q q q q
-0.075 -0.5 -0.6 -1
q q q q q q q q q q q q q
PSRR
Power Supply Rejection Ratio (Note 5) Output Voltage Swing High Output Voltage Swing Low
116 4.99 4.93 17 120 50 300
mV mV
6915f
3
LTC6915
ELECTRICAL CHARACTERISTICS
SYMBOL V+ PARAMETER
REF = 200mV
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
CONDITIONS No Load at OUT, VCM = 200mV No Load at OUT, Capacitive Load at DOUT (CL) = 15pF, Continuous CLK Frequency = 4MHz, CS = LOW, Gain Control Code = 0001 VSHDN = 4.5V (Hardware Shutdown) VSHDN = 1V, Gain Control Code = 0000 (Software Shutdown)
q q
MIN
TYP 0.95 1.4
MAX 1.48 2
UNITS mA mA
= 5V, V - = 0V, V
Supply Current, Parallel Mode Supply Current, Serial Mode (Note 6)
Supply Current, Shutdown
q q q q q
2 135 4.5
10 200
A A V
SHDN Input High SHDN Input Low SHDN and HOLD_THRU Input Current (Note 2) Internal Op Amp Gain Bandwidth Slew Rate Internal Sampling Frequency V + = 5V, V- = -5V, VREF = 0V Gain Error (Note 2) Gain Error (Note 2) Gain Error (Note 2) Gain Error (Note 2) Gain Nonlinearity VOS Input Offset Voltage (Note 3) Average Input Offset Drift (Note 3) IOS CMRR Average Input Bias Current (Note 4) Average Input Offset Current (Note 4) Common Mode Rejection Ratio AV = 1 (RL = 10k) AV = 2 to 32 (RL = 10k) AV = 64 to 1024 (RL = 10k) AV = 2048, 4096 (RL = 10k) AV = 1 VCM = 0mV TA = -40C to 85C TA = 85C to 125C VCM = 1V VCM = 1V AV = 1024, VCM = -5V to 5V, LTC6915C AV = 1024, VCM = -4.9V to 4.9V, LTC6915I AV = 1024, VCM = -5V to 5V, LTC6915I AV = 1024, VCM = -4.9V to 4.9V, LTC6915H AV = 1024, VCM = -5V to 4.97V, LTC6915H VS = 2.7V to 11V Sourcing 200A Sourcing 2mA Sinking 200A Sinking 2mA No Load, VCM = 200mV No Load at OUT, Capacitive Load at DOUT (CL) = 15pF, Continuous CLK Frequency = 4MHz, CS = LOW, Gain Control Code = 0001 VSHDN = 4V (Hardware Shutdown) VSHDN = 1V, Gain Control Code = 0000 (Software Shutdown )
1 5 200 0.2 3
V A kHz V/s kHz
q q q q q
-0.075 -0.5 -0.6 -1
0 0 -0.1 -0.2 3 5
0.075 0.5 0.6 1 15 20 50 100
% % % % ppm nV nV/C nV/C nA nA dB dB dB dB dB dB V V
q q q q q q q q q q q q q q q q
4 1.5 105 105 100 100 90 110 4.97 4.90 123 123 123
10 3
PSRR
Power Supply Rejection Ratio (Note 5) Output Voltage Swing High Output Voltage Swing Low Supply Current, Parallel Mode Supply Current, Serial Mode (Note 6)
116 4.99 4.96 -4.98 -4.90 1.1 1.73 -4.92 -4.70 1.6 2.48
mV mV mA mA
Supply Current, Shutdown
q q q q
160 4
25 240
A A V
SHDN Input High SHDN Input Low
1
V
6915f
4
LTC6915
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
SYMBOL PARAMETER SHDN and HOLD_THRU Input Current (Note 2) Internal Op Amp Gain Bandwidth Slew Rate Internal Sampling Frequency Digital I/O, All Digital I/O Voltage Referenced to DGND VIH VIL VOH VOL Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Timing, V + = 2.7V to 4.5V, V - t1 t2 t3 t4 t5 t6 t7 t8 t9 t1 t2 t3 t4 t5 t6 t7 t8 t9 t1 t2 t3 t4 t5 t6 t7 t8 t9 = 0V (Note 7)
q q q q q q q q q
ELECTRICAL CHARACTERISTICS
V + = 5V, V- = -5V, VREF = 0V
CONDITIONS
q
MIN
TYP
MAX 5
UNITS A kHz V/s kHz V
200 0.2 3 2.0 0.8 V+ - 0.3 0.3 2 60 0 100 100 60 60 30 125 0 30 0 50 50 40 40 20 85 0 30 0 50 50 40 40 20 85 0
V V V A ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
6915f
Sourcing 500A Sinking 500A V+ = 5V, V- = -5V, V
IN = 0V to 5V
q q q
DIN Valid to CLK Setup DIN Valid to CLK Hold CLK Low CLK High CS/LD Pulse Width LSB CLK to CS/LD CS/LD Low to CLK DOUT Output Delay CLK Low to CS/LD Low DIN Valid to CLK Setup DIN Valid to CLK Hold CLK Low CLK High CS/LD Pulse Width LSB CLK to CS/LD CS/LD Low to CLK DOUT Output Delay CLK Low to CS/LD Low DIN Valid to CLK Setup DIN Valid to CLK Hold CLK High CLK Low CS/LD Pulse Width LSB CLK to CS/LD CS/LD Low to CLK DOUT Output Delay CLK Low to CS/LD Low CL = 15pF CL = 15pF CL = 15pF
q q
Timing, V+ = 4.5V to 5.5V, V - = 0V (Note 7)
q q q q q q q q q
Timing, Dual 4.5V to 5.5V Supplies (Note 7)
q q q q q q q q q
5
LTC6915
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: These parameters are tested at 5V supply; at 3V and 5V supplies they are guaranteed by design. Note 3: These parameters are guaranteed by design. Thermocouple effects preclude measurement of these voltage levels in high speed automatic test systems. VOS is measured to a limit set by test equipment capability. Note 4: If the total source resistance is less than 10k, no DC errors result from the input bias current or mismatch of the input bias currents or the mismatch of the resistances connected to IN - and IN+. Note 5: The PSRR measurement accuracy depends on the proximity of the power supply bypass capacitor to the device under test. Because of this, the PSRR is 100% tested to relaxed limits at final test. However, their values are guaranteed by design to meet the data sheet limits. Note 6: Supply current is dependent on the clock frequency. A higher clock frequency results in higher supply current. Note 7: Guaranteed by design, not subject to test.
TYPICAL PERFOR A CE CHARACTERISTICS
Input Offset Voltage vs Input Common Mode
0 -2
INPUT OFFSET VOLTAGE (V)
INPUT OFFSET VOLTAGE (V)
-4 -6 AV = 4096 -8 -10 -12 AV = 1 -14 -16 0 2.5 1.0 1.5 2.0 0.5 INPUT COMMON MODE VOLTAGE (V) 3.0 AV = 256 AV = 16
INPUT OFFSET VOLTAGE (V)
VS = 3V VREF = 0.2V TA = 25C
Input Offset Voltage vs Input Common Mode
20 15
INPUT OFFSET VOLTAGE (V)
INPUT OFFSET VOLTAGE (V)
INPUT OFFSET VOLTAGE (V)
VS = 3V VREF = 0.2V AV = 16
10 5 0 -5 -10 -15 -20 0 TA = 25C TA = 125C TA = 85C TA = 70C TA = -50C 2.5 1.0 1.5 2.0 0.5 INPUT COMMON MODE VOLTAGE (V) 3.0
6
UW
6915 G01 6915 G04
Input Offset Voltage vs Input Common Mode
2 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 AV = 1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 INPUT COMMON MODE VOLTAGE (V)
6915 G02
Input Offset Voltage vs Input Common Mode
8 6 4 2 0 -2 -4 -6 -8 -10 -12 -14 AV = 1 -5 -4 -3 -2 -1 0 1 2 3 4 INPUT COMMON MODE VOLTAGE (V) 5 AV = 256 AV = 16 AV = 4096 VS = 5V VREF = 0V TA = 25C
VS = 5V VREF = 0.2V TA = 25C
AV = 4096 AV = 256
AV = 16
6915 G03
Input Offset Voltage vs Input Common Mode
20 15 10 5 0 -5 -10 -15 TA = -50C -20 0 2 3 1 4 INPUT COMMON MODE VOLTAGE (V) 5 TA = 25C TA = 70C TA = 85C TA = 125C VS = 5V VREF = 0.2V AV = 16 20 15 10 5 0 -5 -10 -15 -20
Input Offset Voltage vs Input Common Mode
VS = 5V VREF = 0V AV = 16
TA = -50C TA = 25C TA = 125C
TA = 85C TA = 70C
-25 -5
3 -3 1 -1 INPUT COMMON MODE VOLTAGE (V)
5
6915 G05
6915 G06
6915f
LTC6915 TYPICAL PERFOR A CE CHARACTERISTICS
Error Due to Input RS vs Input Common Mode
10 0 RS = 5k 20 VS = 5V VREF = 0.2V R+ = R- = RS CIN < 100pF AV = 16 TA = 25C RS = 20k
ADDITIONAL OFFSET (V)
ADDITIONAL OFFSET (V)
ADDITIONAL OFFSET (V)
-10 -20 RS = 15k
RS = 20k -30 VS = 3V RS VREF = 0.2V + R+ = R- = RS CIN -40 CIN < 100pF - AV = 16 RS TA = 25C -50 2.5 0 1.0 1.5 2.0 0.5 INPUT COMMON MODE VOLTAGE (V)
Error Due to Input RS Mismatch vs Input Common Mode
80 VS = 3V = 0.2V V 60 REF CIN < 100pF R+ = 0k, R- = 20k A = 16 40 V TA = 25C R+ = 0k, R- = 15k 20 0 -20 R+ -40 CIN -60 R -80 0
-
ADDITIONAL OFFSET (V)
ADDITIONAL OFFSET (V)
ADDITIONAL OFFSET (V)
R+ = 15k, R- = 0k + - R+ = 20k, R- = 0k 3.0
2.5 1.0 1.5 2.0 0.5 INPUT COMMON MODE VOLTAGE (V)
Offset Voltage vs Temperature
15 2
INPUT OFFSET VOLTAGE (V)
10 VS = 5V -3
VOS (V)
-8
VOS (V)
5
0 VS = 3V -5
-10 -50
-25
50 25 0 75 TEMPERATURE (C)
UW
RS = 10k
6915 G07 6915 G10
Error Due to Input RS vs Input Common Mode
20
Error Due to Input RS vs Input Common Mode
VS = 5V VREF = 0V R+ = R- = RS CIN < 100pF AV = 16 TA = 25C
RS = 20k RS = 10k RS = 15k RS = 5k RS
10
RS = 10k RS = 15k RS = 5k
10
0
0
-10
RS CIN + - 5
-10 CIN RS -5
+ -
-20 3.0
RS 0 1 3 4 2 INPUT COMMON MODE VOLTAGE (V)
-20
-3 1 3 -1 INPUT COMMON MODE VOLTAGE (V)
5
6915 G08
6915 G09
Error Due to Input RS Mismatch vs Input Common Mode
40 VS = 5V 30 VREF = 0.2V CIN < 100pF 20 AV = 16 TA = 25C 10 0 -10 R+ -20 CIN -30 R -40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 INPUT COMMON MODE VOLTAGE (V)
6915 G11
Error Due to Input RS Mismatch vs Input Common Mode
30 VS = 5V VREF = 0V 20 CIN < 100pF AV = 16 TA = 25C 10 0 -10 -20
R+ = 0k, R- = 20k R+ = 0k, R- = 15k
R+ = 0k, R- = 20k R+ = 0k, R- = 15k R+ = 15k, R- = 0k + - 5 R+ = 20k, R- = 0k
R = 15k, R = 0k + - R+ = 20k, R- = 0k
+
-
R+ CIN R-
-
-30
-5 -4 -3 -2 -1 0 1 2 3 4 INPUT COMMON MODE VOLTAGE (V)
6915 G12
VOS vs REF (Pin 13)
VIN = VIN = REF AV = 16 TA = 25C
+ -
VOS vs REF (Pin 13)
20 10 0 VS = 10V -10 -20 -30 VIN+ = VIN- = REF AV = 16 TA = 25C
VS = 5V
-13
VS = 3V
VS = 5V
100
125
-18
0
0.5
1.0
1.5
2.5 VREF (V)
2.0
3.0
3.5
4.0
-40
0
1
2
3
4
56 VREF (V)
7
8
9
10
6915 G13
6915 G14
6915 G15
6915f
7
LTC6915 TYPICAL PERFOR A CE CHARACTERISTICS
Gain Nonlinearity at Gain = 1 (Gain Nonlinearity Decreases for Gain > 1)
5 VS = 2.5V 4 VCM = VREF = 0V R = 10k 3 AL = 1 V 2 TA = 25C 1 0 -1 -2 -3 -4 -5 -2.4 -1.8 -1.2 -0.6 0 0.6 1.2 OUTPUT VOLTAGE (V) 1.8 2.4 1.15 1.10
SUPPLY CURRENT (mA)
GAIN NONLINEARITY (ppm)
0.95 0.90 0.85 0.80 0.75 0.70
TA = 125C TA = 0C TA = -50C
CMRR (db)
Input Voltage Noise Density vs Frequency
300
INPUT REFERRED NOISE DENSITY (nV/Hz) INPUT REFFERED NOISE VOLTAGE (V)
250 200 150 100 50 0
VS = 5V VS = 5V VS = 3V
2 1 0 -1 -2 -3
INPUT REFFERED NOISE VOLTAGE (V)
AV = 16 TA = 25C
1
10
100 1000 FREQUENCY (Hz)
Output Voltage Swing vs Output Current
5.0 4.5
OUTPUT VOLTAGE SWING (V)
TA = 25C
VS = 5V, SOURCING
OUTPUT VOLTAGE SWING (V)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0.01 VS = 3V, SINKING VS = 5V, SINKING VS = 3V, SOURCING
2 1 0 -1 -2 -3 -4 SINKING 1 0.1 OUTPUT CURRENT (mA) 10
6915 G23
SETTLING TIME (ms)
1 0.1 OUTPUT CURRENT (mA)
8
UW
6915 G16 6915 G19 6915 G22
Supply Current vs Supply Voltage
130 TA = 85C 120 110 100
CMRR vs Frequency
VS = 3V, 5V, 5V VIN = 1VP-P R+ = R- = 1k
1.05 1.00
R+ = R- = 10k R+ = 10k, R- = 0k
90 80
R+ + - R- 1 R+ = 0k, R- = 10k 10 100 FREQUENCY (Hz) 1000
6915 G18
70 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 SUPPLY VOLTAGE (V)
6915 G17
Input Referred Noise in 10Hz Bandwidth
3 VS = 3V TA = 25C 3 2 1 0 -1 -2 -3
Input Referred Noise in 10Hz Bandwidth
VS = 5V TA = 25C
10000
0
2
4
6 TIME (s)
8
10
6915 G20
0
2
4
6 TIME (s)
8
10
6915 G21
Output Voltage Swing vs Output Current
5 4 3 6 5 4 3 2 1 VS = 5V TA = 25C 8 SOURCING 7
Low Gain Settling Time vs Settling Accuracy
VS = 5V dVOUT = 1V G 100 TA = 25C
10
-5 0.01
0 0.0001
0.01 0.001 SETTLING ACCURACY (%)
0.1
6915 G24
6915f
LTC6915 TYPICAL PERFOR A CE CHARACTERISTICS
Settling Time vs Gain
35 30 VS = 5V dVOUT = 1V 0.1% ACCURACY TA = 25C
ADDITIONAL GAIN ERROR (%)
SETTLING TIME (ms)
25 20 15 10 5 0
CLOCK FREQUENCY (kHz)
1
10
100 GAIN (V/V)
1000
PI FU CTIO S
(DFN/GN Packages)
IN- (Pin 1/Pin 2): Inverting Analog Input. SHDN (Pin 1 GN Package Only): Shutdown Pin. The IC is shut down when SHDN is tied to V +. An internal current source pulls this pin to V - when floating. IN+ (Pin 2/Pin 3): Noninverting Analog Input. V- (Pin 3/Pin 4): Negative Supply. CS(D0) (Pin 4/Pin 6): TTL Level Input. When in serial control mode, this pin is the chip select input (active low); in parallel control mode, this pin is the LSB of the parallel gain control code. DIN(D1) (Pin 5/Pin 7): TTL Level Input. When in serial control mode, this pin is the serial input data; in parallel mode, this pin is the second LSB of the parallel gain control code. HOLD_THRU (Pin 5 GN Package Only): TTL Level Input for Parallel Control Mode. When HOLD_THRU is high, the parallel data is latched in an internal D-latch. CLK(D2) (Pin 6/Pin 8): TTL Level Input. When in serial control mode, this pin is the clock of the serial interface; in parallel mode, this pin is the third LSB of the parallel gain control code. DOUT(D3) (Pin 7/Pin 9): TTL Level Input. When in serial control mode, this pin is the output of the serial data; in parallel mode, this pin is the MSB of the 4-bit parallel gain
UW
6915 G25
Internal Clock Frequency vs Supply Voltage
3.40 3.35 3.30 TA = 125C 3.25 TA = 85C 3.20 3.15 TA = 25C
10000
Additional Gain Error vs Load Resistance
0.1
0
-0.1
AV = 16 AV = 256
-0.2
-0.3 AV = 4096
TA = -55C 8.5 SUPPLY VOLTAGE (V) 6.5 10.5
6915 G26
3.10 2.5
4.5
-0.4 0 2 6 8 4 LOAD RESISTANCE RL (k) 10
6915 G27
U
U
U
control code. In parallel mode operation, if the data in to DOUT (Pin 9) is from a voltage source greater than V+ (Pin 12), then connect a resistor between the voltage source and DOUT to limit the current into Pin 9 to 5mA or less. DGND (Pin 8/Pin 10): Digital Ground. PARALLEL_SERIAL (Pin 9/Pin 11): Interface Selection Input. When tied to V+, the interface is in parallel mode, i.e., the PGA gain is defined by the parallel codes (D3 ~ D0), i.e., CS(D0), DATA(D1), CLK(D2), and D OUT(D3). When PARALLEL_SERIAL pin is tied to V -, the PGA gain is set by the serial interface. REF (Pin 10/Pin 13): Voltage Reference for PGA output. OUT (Pin 11/Pin 15): Amplifier Output. The typical current sourcing/sinking of the OUT pin is 1mA. For minimum gain error, the load resistance should be 1k or greater (refer to the Output Voltage Swing vs Output Current and Gain Error vs Load Resistance in the Typical Performance Characteristics section). V+ (Pin 12/Pin 16): Positive Supply. SENSE (Pin 14 GN Package Only): Sense Pin. When the PGA drives a low resistance load and the interconnect resistance between the OUT pin and the load is not negligible, tying the SENSE pin as close as possible to the load can improve the gain accuracy.
6915f
9
LTC6915
BLOCK DIAGRA S
(GN Package Only)
3
PARALLEL_SERIAL
DOUT(D3)
PARALLEL_SERIAL
DOUT(D3)
10
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IN +
+
15 CS CH OUT SENSE
IN -
2
-
CF GAIN CONTROL RESISTOR ARRAY
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13 11 4-BIT LATCH 5
REF
MUX 6 7 8 9
HOLD_THRU
1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 8-BIT SHIFT-REGISTER 16 10 4
6915 BD01
CS(D0) DIN(D1) CLK(D2)
SHDN V+ DGND V-
(DFN Package Only)
IN + 2
+
11 CS CH OUT
IN -
1
-
CF GAIN CONTROL RESISTOR ARRAY 10 REF
9 4-BIT LATCH DGND Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 8-BIT SHIFT-REGISTER 12 8 3
6915 BD02
MUX 4 5 6 7
CS(D0) DIN(D1) CLK(D2)
V+ DGND V-
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LTC6915 TI I G DIAGRA
t1 t2 CLK t9
DIN
CS/LD t8 D4 PREVIOUS BYTE D3 D2 D1 D0 D7 * * * * D4 CURRENT BYTE D3
6915 TD
DOUT
OPERATIO
Theory of Operation (Refer to Block Diagrams) The LTC6915 uses an internal capacitor (CS) to sample a differential input signal riding on a DC common mode voltage (the sampling rate is 3kHz and the input switch-on resistance is 1k to 2k, depending on the power supply voltage). This capacitor's charge is transferred to a second internal hold capacitor (CH) translating the common mode voltage of the input differential signal to that of REF pin. The resulting signal is amplified by a zero-drift op amp in the noninverting configuration. Gain control within the amplifier occurs by switching resistors from a matched resistor array. The LTC6915 has 14 levels of gain, controlled by the parallel or serial interface. A feedback capacitor CF helps to reduce the switching noise. Due to the input sampling, an LTC6915 may produce aliasing errors for input signals greater than 1.5kHz (one half the 3kHz sampling frequency). However, if the input signal is bandlimited to less than 1.5kHz then an LTC6915 is useful as instrumentation or as a differential to single-ended AC amplifier with programmable gain. Parallel Interface As shown in Figure 1, connecting PARALLEL_SERIAL to V+ allows the gain control code to be set through the parallel lines (D3, D2, D1, D0). When HOLD_THRU is low
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Timing Diagram of the Serial Interface
t4 t3 t6 t7 D3 D2 D1 D0 D7 * * * * D4 D3 t5
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(referenced to DGND) or floating, the parallel gain control bits (D3 ~ D0) directly control the PGA gain. When HOLD_THRU is high, the parallel gain control bits are read into and held by a 4-bit latch. Any change at D3 ~ D0 will not affect the PGA gain when HOLD_THRU is high. Note that the DFN12 package does not have the HOLD_THRU pin. Instead, it is tied to DGND internally. The DOUT(D3) pin is bidirectional (output in serial mode, input in parallel mode). In parallel mode, the voltage at DOUT(D3) cannot exceed V+; otherwise, large currents can be injected to V+ through the parasitic diode (see Figure 2). Connecting a 10k resistor at the DOUT(D3) pin if parallel mode is selected (see Figure 1) is recommended for current limiting. Serial Interface Connecting PARALLEL_SERIAL to V - allows the gain control code to be set through the serial interface. When CS is low, the serial data on DIN is shifted into an 8-bit shiftregister on the rising edge of the clock, with the MSB transferred first (see Figure 3). Serial data on DOUT is shifted out on the clock's falling edge. A high CS will load the 4 LSBs of the shift-register into a 4-bit D-latch, which are the gain control bits. The clock is disabled internally when CS is pulled high. Note: CLK must be low before CS is pulled low to avoid an extra internal clock pulse.
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LTC6915
OPERATIO
DOUT is always active in serial mode (never tri-stated). This simplifies the daisy chaining of the multiple devices. DOUT cannot be "wire-or" to other SPI outputs. In addition, DOUT does not return to zero at the end of transmission, i.e. when CS is pulled high. A LTC6915 may be daisy-chained with other LTC6915s or other devices having serial interfaces by connecting the
5V LTC6915 SHDN IN - IN+ V- HOLD_THRU CS(D0) DIN(D1) V+ OUT SENSE REF NC P/S DGND 1 0.1F 2 VOUT VIN 3 4 5 HOLD_THRU D0 P D1 D2 D3 PARALLEL GAIN CONTROL CODE = 1010 VOUT = 29 VIN = 512VIN GAIN IS SET BY MICROPROCESSOR. A 10k RESISTOR ON DOUT(D3) PROTECT THE DEVICE WHEN VD3 > V +
6915 F01
VIN
(INTERNAL NODE)
Figure 2. Bidirectional Nature of DOUT/D3 Pin
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DOUT to the DIN of the next chip while CLK and CS remain common to all chips in the daisy chain. The serial data is clocked to all the chips then the CS signal is pulled high to update all of them simultaneously. Figure 4 shows an example of two LTC6915s in a daisy chained SPI configuration.
5V LTC6915 SHDN IN- IN+ V- V+ OUT SENSE REF NC P/S DGND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 10k VOUT 0.1F 6 CS(D0) 7 DIN(D1) 8 CLK(D2) DOUT(D3) CLK(D2) DOUT(D3)
Figure 1. PGA in the Parallel Control Mode
V+
4-BIT GAIN CONTROL CODE CS 4-BIT LATCH
DOUT(D3)
DIN
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 8-BIT SHIFT-REGISTER
DGND
V-
DOUT
6915 F01
CLK
(D3)
6915 F02
Figure 3. Diagram of Serial Interface (MSB First Out)
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LTC6915
OPERATIO
CLK
DIN
D15
CS/LD
6915 F04
The amplifier's gain is set as follows:
D3, D2, D1, D0 Gain 0000 0 0001 1 0010 2 0011 4 0100 8 0101 16 0110 32 0111 64 1000 128 1001 256 1010 512 1011 1024 1100 2048 1101~ 1111 4096
Input Voltage Range The input common mode voltage range of the LTC6915 is rail-to-rail. However, the following equation limits the size of the differential input voltage: V - (VIN+ - VIN -) + VREF V+ - 1.3 Where VIN+ and VIN- are the voltage of the differential input pins, V+ and V - are the positive and negative supply voltages respectively and VREF is the voltage of REF pin. In addition, VIN+ and VIN- must not exceed the power supply voltages, i.e., V - < VIN+ < V+ and V - < VIN- < V+
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1 0.1F 2 VIN -5V 0.1F CS P DIN CLK 5 HOLD_THRU 6 CS(D0) 7 DIN(D1) 8 CLK(D2) DOUT(D3) DGND P/S NC 3 4 LTC6915 SHDN #1 IN- IN+ V- V+ OUT SENSE REF 16 15 14 13 12 11 10 9 -5V -5V 0.1F 0.1F VOUT 1 0.1F 2 VIN 3 4 5 6 7 8 LTC6915 SHDN #2 IN - IN+ V- HOLD_THRU CS(D0) DIN(D1) V+ OUT SENSE REF NC P/S DGND 16 15 14 13 12 11 10 9 DOUT -5V VOUT 0.1F CLK(D2) DOUT(D3) D11 D10 D9 D8 D7 D3 D2 D1 D0 GAIN CODE FOR #2 GAIN CODE FOR #1
Figure 4. 2 PGAs in a Daisy Chain
5 Volt Operation When using the LTC6915 with supplies over 5.5V, care must be taken to limit the maximum difference between any of the input pins (IN+ or IN- ) and the REF pin to 5.5V, i.e., |VIN + - VREF| < 5.5 and |VIN- - VREF| < 5.5 If not, the device will be damaged. For example, if rail-torail input operation is desired when the supplies are at 5V, the REF pin should be 0, 0.5V. As a second example, if the V+ pin is 10V, and the V - and REF pins are at 0, the inputs should not exceed 5.5V.
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LTC6915
OPERATIO
Settling Time The sampling rate is 3kHz and the input sampling period during which CS is charged to the input differential voltage, VIN, is approximately 150s. First assume that on each input sampling period, CS is charged fully to VIN . Since CS = CH (= 1000pF), a change in the input will settle to N bits of accuracy at the op amp noninverting input after N clock cycles or 333s(N). The settling time at the OUT pin is also affected by the internal op amp. Since the gain bandwidth of the internal op amp is typically 200kHz, the settling time is dominated by the switched-capacitor front end for gains below 100 (see the Low Gain Settling Time vs Settling Accuracy and the Settling Time vs Gain graphs in the Typical Performance Characteristics section). In addition, the worst case settling time after a device-enable (active low on Pin 1 of a GN package) is equal to the settling due to the gain plus the input settling time (333s * N). For example, if an LTC6915 is enabled with a logic high on Pin 1 then, the maximum settling time to 10 bits of accuracy (0.1%) and a gain equal to 100 is 8.33ms ([333s * 1024] + 5ms). Input Current Whenever the differential input VIN changes, CH must be charged up to the new input voltage via CS. This results in an input charging current during each input sampling period. Eventually, CH and CS will reach VIN and ideally, the input current would go to zero for DC inputs. In reality, there are additional parasitic capacitors which disturb the charge on CS every cycle even if VIN is a DC voltage. For example, the parasitic bottom plate capacitor on CS must be charged from the voltage on the REF pin to the voltage on the IN- pin every cycle. The resulting input charging current decays exponentially during each input sampling period with a time constant equal to RSCS. If the voltage disturbance due to these currents settles before the end of the sampling period, there will be no errors due to source resistance or the source resistance mismatch between IN+ and IN-. With RS less than 10k, no DC errors occur due to input current mismatch. In the Typical Performance Characteristics section of this data sheet, there are curves showing the additional error from non-zero source resistance in the inputs. If there are no large capacitors across the inputs, the amplifier is less sensitive to source resistance and source resistance mismatch. When large capacitors are placed across the
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inputs, the input charging currents are placed across the inputs. The input charging currents described above result in larger DC errors, especially with source resistor mismatches. Power Supply Bypassing In a dual supply operation, connect a 0.1F bypass capacitor from each power supply pin (V+ and V-) to an analog round plance surrounding an LTC6915. The bypass capacitor trace to the supply pins must be less than 0.2 inches (an X7R or X5R capacitor type is recommended). In single supply operation, connect the V- pin to the analog ground plane and bypass the V+ pin. Shutdown Modes The IC has two shutdown modes, hardware shutdown and software shutdown. When SHDN is tied to V+, the IC is in hardware shutdown mode. During this shutdown mode, the gain setting digital interface (serial or parallel) and the main op amp are both disabled, thus the PGA dissipates very small supply current (see the Electrical Characteristic table). When SHDN is floating, an internal current source will pull it down to V -. The digital interface is turned on to read the gain setting codes. The IC is in normal amplification mode as long as the gain control code is other than 0000. If the gain control code is 0000, the IC operates in software shutdown mode, i.e., the main op amp is turned off so that the PGA dissipates less power. The DFN package does not have hardware shutdown. Setting the Voltage at the REF Pin The current coming out of the REF pin may affect the reference voltage at the REF pin (VREF). If VREF is set by a resistive divider then the VREF voltage is a function of the VOUT voltage (see Figure 5). In order to minimize the VREF variations, the total resistance of R1 plus R2 should be much less than 32k (5k or less) or use a voltage reference to set VREF.
LTC6915
+
OUT VOUT
V+ R1
-
R = 32k REF V - VREF IREF = OUT 32k VREF
0.1F R2 V-
6915 F05
V+ V V- VREF = + OUT + * (R1 R2 32k) R1 32k R2
Figure 5
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LTC6915
TYPICAL APPLICATIO
Multiplexing Two LTC6915's
Send a gain code of 0000 to one IC to set its output to a high impedance state and send a gain code other than 0000 to the second IC to set it for normal amplification. If both devices are ON, the 200 resistors protect the outputs. The sense pin connection maintains gain accuracy for loads 1k or greater.
PACKAGE DESCRIPTIO
3.40 0.05 1.70 0.05 2.24 0.05 (2 SIDES)
0.25 0.05 3.30 0.05 (2 SIDES) 0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M0-229 2. ALL DIMENSIONS ARE IN MILLIMETERS
.045 .005
.254 MIN
.150 - .165 .229 - .244 (5.817 - 6.198) .150 - .157** (3.810 - 3.988) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
.0165 .0015
.0250 TYP 1 .015 .004 x 45 (0.38 0.10) .053 - .068 (1.351 - 1.727) 23 4 56 7 8 .004 - .0098 (0.102 - 0.249)
RECOMMENDED SOLDER PAD LAYOUT
.007 - .0098 (0.178 - 0.249) .016 - .050 (0.406 - 1.270)
0 - 8 TYP
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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5V 0.1F SHDN V+ LTC6915 #1 IN- OUT VIN1 IN+ V
-
5V 0.1F 200 VIN2 SENSE REF NC -5V -5V 0.1F SHDN V+ LTC6915 200 #2 IN- OUT IN+ V
-
SENSE REF NC -5V
VOUT
-5V 0.1F
HOLD_THRU CS DIN
HOLD_THRU CS DIN CLK
PAR_SER DGND DOUT
PAR_SER DGND DOUT
DATA P SELECT (TTL LEVELS) CLOCK
CLK
6915 F06
Figure 6. A 2:1 Multiplexing Two LTC6915's with Daisy Chained Gain Control DE/UE Package 12-Lead Plastic DFN (4mm x 3mm)
(Reference LTC DWG # 05-08-1695)
4.00 0.10 (2 SIDES) 0.58 0.05 R = 0.20 TYP 3.00 0.10 (2 SIDES) 1.70 0.10 (2 SIDES) PIN 1 NOTCH
(UE12/DE12) DFN 0802
7
R = 0.115 TYP
0.38 0.10 12
PIN 1 TOP MARK PACKAGE OUTLINE 0.200 REF
0.75 0.05
6 0.25 0.05 3.30 0.10 (2 SIDES)
1 0.50 BSC
0.00 - 0.05
BOTTOM VIEW--EXPOSED PAD 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 4. EXPOSED PAD SHALL BE SOLDER PLATED
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF
.008 - .012 (0.203 - 0.305)
.0250 (0.635) BSC
GN16 (SSOP) 0502
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LTC6915
TYPICAL APPLICATIO
V+ C5 0.1F
10k ZETEK ZXM61P02F R < 10K 16 MOSI 15 MISO 14 SCLK 13 CS1 12 CS2
9 X1 4MHz 10
20 VDD PIC16LF73 RC5/SDO OSC1/ RC4/SDI/SDA CLKIN RC3/SCK/SCL OSC2/ CLKOUT RC2/CCP1 RC1/T1OSI/CCP2
V+
1
28 RB7 MCLR/ 7 RAS/AN4/SS VPP 6 RA4/T0CLK1 VSS VSS 8 19
10k V+
Figure 7. Bridge Amplifier with Programmable Gain and Analog to Digital Conversion. (Standby Current Less than 100A)
RELATED PARTS
PART NUMBER LTC1043 LTC1100 LTC1101 LTC1167 LTC1168 LTC1789-1 LTC2050 LTC2051 LTC2052 LTC2053 LTC6800 DESCRIPTION Dual Precision Instrumentation Switched-Capacitor Building Block Precision Zero-Drift Instrumentation Amplifier Precision, Micropower, Single Supply Instrumentation Amplifier Single Resistor Gain Programmable, Precision Instrumentation Amplifier Low Power Single Resistor Gain Programmable, Precision Instrumentation Amplifiers Single Supply, Rail-to-Rail Output, Micropower Instrumentation Amplifier Zero-Drift Operational Amplifier Dual Zero-Drift Operational Amplifier Quad Zero-Drift Operational Amplifier Rail-to-Rail Input and Output, Zero-Drift Instrumentation Amplifier with Resistor-Programmable Gain Rail-to-Rail Input and Output, Instrumentation Amplifier with Resistor-Programmable Gain COMMENTS Rail-to-Rail Input, 120dB CMRR Fixed Gains of 10 or 100, 10V Offset, 50pA Input Bias Current Fixed Gain of 10 or 100, IS < 105A Single Gains Set Resistor, G = 1 to 10,000 Low Noise: 7.5nV/Hz IS = 530A IS = 80A Max SOT-23 Package MS8 Package GN16 Package MS8 Package, 10V Max VOS, 50nV/C Max Drift MS8 Package, 100V Max VOS, 250nV/C Max Drift
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507 q www.linear.com
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V+ BRIDGE SENSOR C1 0.1F C2 0.1F 1 2 3 4 5 6 7 8 SHDN IN - IN+ V- HOLD_THRU CS(D0) DIN(D1) CLK(D2) LTC6915 OUT SENSE REF NC V+ 16 15 14 13 2 12 3 11 4 10 9 GND 6 1.25V 5 IN+ IN - REF - REF+ LTC2431 SCK CS FO 1 VCC SDO 8 9 7 10 PAR_SER DGND DOUT(D3) 0V MEASURE STANDBY V+ C3 0.1F V+ 4 VIN GND1 1 VOUT GND2 2
6915 F07
6 C3 1F
CONTROL SIGNAL
LT1790-1.25
LT/TP 0204 1K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2003

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